1. Field of the Invention
This invention relates generally to a semiconductor memory device, and, more specifically, to a fabrication of a static random access memory (“SRAM”) cell.
2. Description of the Related Art
Semiconductor memory devices have been well-known for many years. Such devices are typically one of two types: volatile memory devices, such as dynamic random access memories (hereinafter “DRAMs”), and non-volatile memory devices, such as static random access memories (hereinafter “SRAMs”). Volatile memory devices will store an electrical charge (hereinafter “EC”) only for a very short period of time, and the electrical charge in the cells must be periodically refreshed. Non-volatile memory devices will normally store data for an indefinite period of time once the data has been written into the memory cells. The cells are designed such that the electrical charge placed in the cell will remain in the cell indefinitely under appropriate conditions. The indefinite storage of the electrical charge is an advantage of the non-volatile memories. The SRAM is a significant memory device due to its high speed, low power consumption, and simple operation. SRAMs are generally used in applications requiring high speed operations, such as a cache memory for a data processing system.
An SRAM chip is conventionally structured in rows and columns of individual SRAM cells. SRAM memory cells are generally comprised of four or six transistor memory cells. A conventional SRAM cell comprises a plurality of word lines and a plurality of pairs of complementary bit lines. Data is read from or written into a selected SRAM cell via the pairs of bit lines. Power may be provided to the SRAM memory cell by a collector common voltage or Vcc.
A goal for SRAM cells in an integrated circuit is a compact layout of transistors and interconnects, but the layout should allow for alignment errors during manufacture and provide isolation between active regions. Additionally, manufacturing should achieve a high yield of operable integrated circuits using a relatively simple process that minimizes manufacturing steps to reduce cost. The layout should provide a robust cell that has minimum junction capacitance and leakage. The layout should also be fast and not subject to errors that came a stored value to erroneously change. For example, reducing the soft error rate (hereinafter “SER”) of a SRAM cell is generally advantageous. SER refers to the upset of data in memory caused by cosmic rays and background radioactive material. Soft errors are potentially harmful to users. A soft error in memory may cause networking equipment to send information packets, such as money transfers, to the wrong address. The layout should also have minimum junction capacitance and leakage. The industry is lacking an efficient memory layout that provides efficient packaging of memory, reduced current leakage, reduced error, etc.
The present invention eliminates or, at least, reduces the aforementioned problems.